1. Field of the Invention
The present invention relates to a D/A converter of switched capacitor type, and a drive circuit for a liquid crystal display.
2. Description of the Related Art
In recent years, with their characteristics of being flat and having low power consumption, liquid crystal display units have been used in the application of large-screen television as well as in such mobile applications as a mobile phone, a notebook personal computer, etc.
Methods of driving such liquid crystal display units are roughly divided into the following two methods: a simple matrix method and an active matrix method.
A simple matrix method is a mechanism wherein conductors are installed like a grid in two directions being orthogonal to each other, and liquid crystal material having anisotropic conductivity is injected into and formed at respective intersections so as to be sandwiched by conductors in the both directions, and liquid crystals at matrix intersections are driven by adjusting timing in a vertical or horizontal direction, respectively, and sending electric signals through the conductors, and quantity of light transmitted through a substrate from an external light source (back light) is adjusted, thus brightness of external pixels is adjusted. While the mechanism has a simple structure, is low in cost, and has a good yield, the simple matrix method suffers from the disadvantage that electrodes of respective liquid crystal cells constituting pixels are not independent, and voltage interferes, which affects cells in the periphery making it difficult to clearly display respective pixels and thus making it impossible to achieve a high contrast.
On the other hand, an active matrix method includes active elements (generally, TFT (Thin Film Transistor) is used) capable of switching control of respective pixels in addition to the structure of the simple matrix method, and individually drives liquid crystals located at respective intersections, by on-off controlling the active elements in a timely manner. According to this method, as respective pixels can be reliably lighted, a clear display screen with high responsivity is possible. Thus, currently, the active matrix method is widely used in computer displays, etc.
FIG. 11 is a block diagram showing schematically typical configuration of a liquid crystal display unit of an active matrix method. A liquid crystal display unit 1 shown in FIG. 11 includes a display control means 2, a data driver 3, a gate driver 4, and a liquid crystal display 5.
The liquid crystal display 5 has two substrates and a liquid crystal sandwiched by the both substrates, wherein a plurality of data lines DL extending in one direction are installed on one substrate, while a plurality of scan lines SL extending in a direction intersecting with the data lines DL are installed on the other substrate. Each data line DL and each scan line SL are configured to be able to be driven and controlled by the data driver 3 and the gate driver 4, respectively. Then, operations of the data driver 3 and the gate driver 4 are controlled by the display control means 2.
At intersection positions of respective data lines DL and respective scan lines SL, pixel circuits 6 are formed like a matrix. As shown in FIG. 11, the pixel circuit 6 includes a TFT 7, a liquid crystal display element 8, a reference terminal 9, and charging capacitor 10. Gate electrodes of the TFTs 7 provided in a plurality of the pixel circuits 6 that are arranged in the same row are connected to a common scan line SL, and driving and controlling of the scan line SL provides on-off control of the TFT 7. Source or drain electrodes of the TFTs 7 provided in the plurality of pixel circuits 6 arranged on the same column are also connected to a common data line. This enables TFT 7 provided in the pixel circuit 6 to become conduction state by driving the data line DL and the scan line SL connected to a target pixel circuit 6, and a voltage potential difference between the reference terminal 9 (such configured that predetermined voltage is applied (or grounded)) and the data line DL is applied to both ends of the charging capacitor 10 of the target pixel circuit 6, and thus charging is performed. Then, voltage at both ends of the charging capacitor 10 controls transmissivity of a liquid crystal display element 8, and thus the pixel control is performed.
FIG. 12 is a block diagram showing schematically typical configuration of the data driver as shown in FIG. 11. The data driver includes a shift register 11, a data register 12, a data latch 13, a level shifter 14, a group of D/A converters 15, and a gray-scale voltage generation circuit 16.
The shift register 11 outputs a shift pulse depending on a dock signal to be inputted. Depending on the shift pulse, the data register 12 sequentially shifts up a video signal inputted from the display control means 2, and distributes the video signal according to the number of outputs. The data latch 13 latches the video signal distributed by the data register 12, and simultaneously outputs all outputs to the level shifter 14, depending on a control signal to be inputted. The level shifter 14 converts voltage swing of the video signal to be inputted into magnitude of the voltage swing corresponding to liquid crystal driving voltage, and outputs the video signal to the group of D/A converters.
The group of the D/A converters 15 includes a plurality of D/A converters, each converter performing D/A conversion based on corresponding digital data to be inputted from the level shifter 14 and outputting to the data line DL through an output terminal 3u. Driving a target data line DL according to the timing of outputting gray-scale signals from this output terminal 3u results in application of gray-scale voltage based on the video signals to the respective pixels connected to the data line DL to be driven, thus providing control corresponding to the gray-scale voltage.
As a D/A converter included in the above-described data driver 3, a D/A converter of switched capacitor type has been used conventionally (see Japanese Unexamined Patent Application No. 2000-13234, for instance).
FIG. 13 is a circuit diagram illustrating schematic configuration of the D/A converter of switched capacitor type having the conventional configuration described in Japanese Unexamined Patent Application No. 2000-13234 (hereinafter abbreviated to a “D/A converter”, as appropriate). The D/A converter 101 as shown in FIG. 13 includes input capacitors C0, C1, . . . Cn having a capacitance ratio corresponding to the number of bits in input digital data (n being the same number as the number of bits in the input digital data) and an output capacitor Cc to be connected to output. The D/A converter 101 further includes an operational amplifier A91 that has a configuration in which the line to which the input capacitor and the output capacitor are connected in parallel shall be inverting input and the line from the reference voltage Vr shall be non-inverting input, switches S1 to Sn that switch connection of level voltages (V1, V2) with the input capacitor depending on the input digital data, and switches Sa1 to Sa5 that switch operation of the D/A converter.
Specifically, as shown in FIG. 13, the switches Sa2 to Sa5 are switches that can be on-off controlled, respectively, while the switches S1 to Sn and the switch Sa1 are switches capable of switching control of connections with H and L, respectively. The switches S1 to Sn are such configured that the level voltage V1 is applied thereto by being connected to the terminal H, and the level voltage V2 is applied thereto by being connected to the terminal L. In addition, the switch Sa1 is configured to be connected with the non-inverting input terminal of the operational amplifier A91 by being connected to the terminal H, and the switch Sa1 is connected with the amplified output terminal of the operational amplifier A91 by being connected to the terminal L.
In order to avoid complexity due to the increasing number of symbols, in the following, the symbols assigned to the respective capacitors shall directly designate a capacitance value of the capacitor, and describe the capacitor symbols and capacitor's capacitance values by same symbols so as not to be confused.
Herein, the input capacitors C0 to Cn shall have the capacitance value satisfying Ci=Cu·2(i−1) (i=1, . . . , n) when n bits of digital data is inputted where the unit capacitance value is Cu. In addition, C0=Cu.
With this configuration, the switch Sa1 shall be H, Sa2 and Sa4 shall be off, Sa3 and Sa5 shall be on, and S1 to Sn shall be L during reset process. Then, point A in FIG. 13 (node of the inverting input terminal of the operational amplifier A91) is given voltage corresponding to Vr+Vos (Vos being offset voltage of the operational amplifier A91). Thus, a total value Q0 of charge amount to be charged to the respective input capacitor and the output capacitor can be expressed in the following formula 1:
                                                                        Q                ⁢                                                                  ⁢                0                            =                            ⁢                                                                    (                                          Vr                      +                      Vos                      -                      Vr                                        )                                    ⁢                  C                  ⁢                                                                          ⁢                  0                                +                …                +                                                      (                                          Vr                      +                      Vos                      -                      Vr                                        )                                    ⁢                  Cn                                +                                                                                                      ⁢                                                (                                      Vr                    +                    Vos                    -                    Vr                                    )                                ⁢                Cc                                                                                        =                            ⁢                              Vos                ·                                  Cu                  ⁡                                      (                                                                  2                        n                                            +                                              Cc                        Cu                                                              )                                                                                                          (        1        )            
Then, during input of digital data, the switch Sa1 shall be L, Sa4 shall be on, Sa2, Sa3 and Sa5 shall be off, and S1 to Sn shall be either H or L depending on the digital data Md to be inputted. For instance, when n=8 and the digital data Md is “11100110”, the switches S2, S3, S5, S6 and S7 shall be H, while the switches S1, S3, S4 shall be L. Then, a total value Q1 of the charge amount to be charged to the respective input capacitor and the output capacitor can be expressed in the following formula 2. However, Mt in the formula 2 shall be a value to be obtained by converting the digital data Md into a decimal number (Mt=230, in the above example). In addition, Vo′ shall be voltage (voltage of an amplified signal) of the amplified output terminal of the operational amplifier A91.
                                                                        Q                ⁢                                                                  ⁢                1                            =                            ⁢                                                                    (                                          Vr                      +                      Vos                      -                                              V                        ⁢                                                                                                  ⁢                        1                                                              )                                    ⁢                                      Mt                    ·                    Cu                                                  +                                                      (                                          Vr                      +                      Vos                      -                                              V                        ⁢                                                                                                  ⁢                        2                                                              )                                    ⁢                                      (                                                                  2                        n                                            -                      Mt                                        )                                    ⁢                  Cu                                +                                                                                                      ⁢                                                (                                      Vr                    +                    Vos                    -                                          Vo                      ′                                                        )                                ⁢                Cc                                                                                        =                            ⁢                                                                    (                                                                  V                        ⁢                                                                                                  ⁢                        2                                            -                                              V                        ⁢                                                                                                  ⁢                        1                                                              )                                    ⁢                                      Mt                    ·                    Cu                                                  +                                                      (                                                                  2                        n                                            +                                              Cc                        Cu                                                              )                                    ⁢                                      Vr                    ·                    Cu                                                  +                                                                                                      ⁢                                                                    (                                                                  2                        n                                            +                                              Cc                        Cu                                                              )                                    ⁢                                      Vos                    ·                    Cu                                                  -                                                      2                    n                                    ⁢                  V                  ⁢                                                                          ⁢                                      2                    ·                    Cu                                                  -                                                      Cc                    Cu                                    ⁢                                                            Vo                      ′                                        ·                    Cu                                                                                                          (        2        )            
Herein, as charges are stored between during the reset process and during the input of digital data, Q0=Q1 is true, and solving this allows Vo′ to be obtained in the following formula 3:
                              Vo          ′                =                  Vr          -                                    Mt              ·              V                        ⁢                                                  ⁢                          1              ·                              Cu                Cc                                              -                                                    (                                                      2                    n                                    -                  Mt                                )                            ·              V                        ⁢                                                  ⁢                          2              ·                              Cu                Cc                                                                        (        3        )            
In fact, with the above operation, the voltage V0′ to be outputted from the output terminal of the operational amplifier A91 shows the value based on the data Mt to be obtained by canceling offset voltage Vos of the operational amplifier A91 and converting the input digital data Md into the decimal number. After this, by turning on the output switch Sa2, output voltage Vout (=Vo′) of magnitude based on the data Mt can be obtained. This may configure the D/A converter of switched capacitor type cap able of canceling offset of an operational amplifier.
In the case of the circuit configuration as described in FIG. 13, the output switch Sa2 in off state is connected to the output side of the operational amplifier A91 during reset process. The output switch Sa2 is designed to control whether or not to apply output voltage to be outputted from the D/A converter to the respective data lines DL for controlling display of liquid crystal element. As described above, the liquid crystal display 5 has a configuration in which the potential difference between the data line DL and the reference terminal 9 generates a voltage at the both ends of the charging capacitor 10 under the state where pixels are being selected, thereby the charging capacitor 10 is charged, and the voltage at the both ends of the charging capacitor 10 allows display of the liquid crystal element 8 to be controlled. Therefore, in order to implement liquid crystal control rapidly, charging should be rapidly performed to the charging capacitor 10. Thus, it is required to increase the size of the output switch Sa2 for applying output voltage for carrying out the charging to the data line DL.
However, when the size of the output switch Sa2 is increased, parasitic capacitance Ca2 (see FIG. 14) residing in the switch Sa2 is also increased. In addition to the input capacitors C0 to Cn and the output capacitor Cc, the parasitic capacitance Ca2 is also charged. However, there is the problem that due to increased size of the parasitic capacity Ca2, time to complete the charging operation will increase when amount of the current flowing in the circuit is same. In addition, when the amount of the current flowing in the circuit is increased in order to shorten the time of the charging operation, there also arises a new problem that power consumption in the D/A converter increase.